1 Mbit Ultra-Low Power SRAM

This project was completed as part of ECE 4332 (Introduction to VLSI Design) at UVA

Contributors

Project Goals

The goal of this project was to design a 1 Mbit SRAM and implement the design using FreePDK's 45nm technology in Cadence Virtuoso, while demonstrating functionality at the following PVT corners:

  • [TT, FF, SS, FS, SF]
  • [0C, 27C, 50C]
  • [VDD - 10%, VDD, VDD + 10%]

The design was to be optimized such that the following figure of merit was minimized:

\[(Active\ energy\ per\ access)^2(Delay)(Area)(Idle\ Power)\]

Approach

The figure of merit equation guided my approach to this design. Since $V_{DD}$ is squared in the active energy equation, which is itself then squared in the design metric, lowering $V_{DD}$ was given the highest priority when making design decisions. I also sought to reduce the active energy per access by structuring large interconnects hierarchically and looking for energy-optimized bitcells in the literature.

Outcomes

Design Outcomes

  • Achieved a figure of merit of $ 2.05 \times 10^{-33} J^2*sec*mm*W$, whereas the historical class average is on the order of $10^{-29}$
  • Measured an extremely low average energy per access of $687$ fJ for the read operation and $875$ fJ for the write operation at $50$ MHz and $V_{DD}=0.4\ V$. Assuming 5 reads for every write, this corresponds to 718 fJ per bit access on average.
  • Attained 1000x energy improvement over initial design by replacing 6T bitcells with dynamic leakage suppression bitcells. Because the design metric emphasized energy, we chose to tradeoff slower access time for lower energy.
  • Recorded an inactive power of $123\ \mu W$ under 27C, TT conditions.
  • Verified memory functionalty at 36 different PVT conditions in Cadence Spectre.

Skill-related Outcomes

  • Practiced self-pacing a months-long project with little direction beyond specification (e.g., setting internal deadlines, putting roadmap into place at beginning of semester)
  • Honed communication skills when team was not working harmoniously by coordinating and mediating a meeting between team members. Generated action items to help course-correct and improve collaboration, ultimately leading to a successful project delivery
  • Improved ability to evaluate design space and make decisions at all levels of system hierarchy to tailor design to application needs
  • Gained experience with schematic capture in Cadence Virtuoso and design verification using Spectre

Report

For more details about the project, check out the report embedded below.